“Stroke” type video display systems, as typically used in cathode ray tube (CRT) video display units in the 1960s and 1970s, drew their images on a “real time” basis to the screen. That is to say, as soon as a graphic display element is defined, it is “stroked” directly to the phosphor face of the CRT, using x-y deflection of an electron beam and “z” video modulation. Such a stroke system has no refresh memory, so the image on the screen is updated and refreshed at the scan rate of the screen, which is typically 60 Hz, or 16.67 msec. While such stroke systems had other problems associated with them, one advantage possessed by such systems is that they were visible in real time—there was zero latency in the displayed image.
To avoid some of the other problems associated the stroke systems, stroke to raster conversion systems were introduced. In a known stroke to raster conversion technique, the real time image previously stroked to the screen is instead “stroked” in a random x-y manner to a random access memory (RAM), in which a “z” video modulation datum is stored in a matrix comprising x, y data addresses that correspond to x, y locations on the raster display screen, which can be an LCD, a plasma screen, a CRT or the like. This type of a “stroke-to-raster” conversion should provide a worse case latency of less than 16.67 msec, that is, less than one scan of the display when operating at 60 Hz, plus from 0 to 16.67 msec additional. The exact amount of the additional latency depends upon the physical location of the video feature on the display screen. When the video feature is located at an x, y address on the display near the first part of the raster pattern, then the additional latency will be very small. However, when the video feature is located near the end of the raster pattern, the additional latency can be almost an entire scan duration, that is, almost 16.67 msec.
An example of one such early stroke-to-raster conversion technique is provided by a double buffered system for a video display, where a pair of memory buffers is provided for the display of sequential video images on a display screen. In such a system, a first “frame” of video data for producing a first video image is stored in a first buffer, from which the video image data are communicated to the display screen. The buffer providing the display image is also often referred to as the “front” buffer. While the first video image is being displayed on the screen, that is, during its frame time, a second buffer, referred to at this point as the “rear” buffer, is used to prepare a second frame for display on the screen. This preparation entails erasing a prior frame of video data from the second buffer and writing the new set of video data in the second buffer.
At the end of the first frame's frame time, a “swap” command logically converts the second buffer into the front buffer, that is, the video data in the second buffer is now communicated to the display screen. The first buffer, converted into the “rear” buffer by the same swap command, erases the first frame of video data and refreshes itself by building a third frame of video data during the frame time for the second frame.
Once the second frame's frame time has elapsed, a new swap command restores the first buffer to its former status as the front buffer and the second buffer to its former status as the rear buffer. During this frame time, the third frame image is displayed from the first buffer, while the second frame is erased and a fourth frame is built in the second buffer. This process is repeated sequentially.
This system may be abstracted to be represented as a system in which two buffers are present during frame time M. One of the buffers contains video image M and displays it to the screen. Simultaneously, the other buffer erases the video data for video image (M−1) and stores the video data for video image (M+1).
An easily recognized problem of the double buffered system is that the image being presently displayed, that is, image M, is “old,” because it was assembled during frame time M−1 and not during frame time M. It will also be recognized that it is the activity in the rear buffer that is generally rate-limiting. While a discrete period of time is required to sweep through the data for display purposes, that is, the so-called “frame period”, the frame time is a longer period, comprising a small integral number of frame periods, allowing the preparation of the subsequent video image. The time from when the storage of a video image starts until when the video image frame is displayed is referred to as “render-to-display latency.” A double buffered system has an inherent latency of one frame time, or, put another way, the inherent latency is N frame periods, when the frame time is N frame periods long.
It is also known to provide more than two buffers, however this can increase latency to greater than one frame time in the absence of artificially imposed constraints.
Exemplary embodiments provide a new method for minimizing the render-to-display latency for a video display system, particularly a video display system as would be used in a very time-critical operation, such as in a display in an instrument such as an avionic instrument.